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STA680
HD RadioTM base-band receiver
Preliminary Data
Features
General

HD Radio signal decoding for AM and FM digital audio TensilicaTM signal/audio processing core architecture running up to 166 MHz Hardware support for conditional access (one-time programmable 640-bit memory) 2 internal PLLs: processor cores and peripheral bus 1 Internal clock oscillator and external clock input Less than 200 mW with core voltage of 1.2 V and I/O voltage of 3.3 V Temperature range: -40 to +85 C
LQFP144 (20x20x1.4 mm) LFBGA 168 balls (12x12x1.4 mm)
Other interfaces
One stereo audio sample rate converter (44.1 kS/s, 45.6 kS/s, 48 kS/s) One input and three stereo channels audio output (by IIS serial audio interface) 2 IIC and 3 SPI serial interfaces 1 UART interface 1 GPIO interface (8 lines) SD/MMC interface via SPI JTAG interface
Memories

Internal boot ROM SDRAM controller addressing up to 512 Mbit of SDRAM in x16 configuration Serial Flash memory interface for application code loading
Supported HD Radio system capabilities

Multicasting Program service data Real-time traffic Audio time shifting iTunes Tagging TM Surround sound
Turner interface

Support of RF-IF peripheral processor (RIPP) and other front ends such as STA3004 and STA7506 Input from RF front-end via programmable serial interface supporting 650 kS/s, 675 kS/s, 744.1875 kS/s, 882 kS/s, 912 kS/s sample rates Secondary RF front-end interface for dual tuner applications Device summary
Order code STA680 STA680Q
Applications

Car radio Personal navigation device (PND) Portable battery operated systems
Table 1.
Package(1) LFBGA 168 balls (12x12x1.4 mm) LQFP144 (20x20mm)
Packing Tray Tray
1. ECOPACK(R) compliant.
July 2008
Rev 1
1/43
www.st.com 1
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Contents
STA680
Contents
1 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 System overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 2.2 2.3 HD Radio processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Dual stream HD Radio processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Additional processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3.1 2.3.2 2.3.3 AM/FM processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Audio codec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Other . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.4
Overview of main functional blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.4.1 2.4.2 2.4.3 2.4.4 2.4.5 Adjacent channel filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 HiFi2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Vectra . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Hardware accelerator (VITERBI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3
I/O description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1 3.2 3.3 3.4 LQFP description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 LFBGA description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 I/Os supply groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4
Operation and general remarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.1 4.2 Clock schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Power on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.2.1 4.2.2 4.2.3 4.2.4 Power supply ramp up phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Oscillator setting time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Boot sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Normal operation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5
Digital I/O and memory interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.1 5.2 Interfaces: LQFP vs. LFBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Tuner interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2/43
STA680
Contents
5.3
Audio interface (AIF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.3.1 5.3.2 5.3.3 5.3.4 Output serial audio interface (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Input serial audio interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 S/PDIF interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Audio sample rate converter (ASRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.4
Serial peripheral interfaces (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.4.1 5.4.2 5.4.3 5.4.4 5.4.5 5.4.6 Host micro serial peripheral interface (SPI1) . . . . . . . . . . . . . . . . . . . . . 31 Flash serial peripheral interface (SPI2) . . . . . . . . . . . . . . . . . . . . . . . . . 32 SD/MMC serial peripheral interface (SPI3) . . . . . . . . . . . . . . . . . . . . . . 32 I2C interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Host micro I2C interface (I2C1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Auxiliary I2C interface (I2C2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.5
SDRAM interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.1 6.2 6.3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7 8
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3/43
List of tables
STA680
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Reference clock configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Power on timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Interface list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Base-band interfaces pin list. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 BBI timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 AIF pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Serial audio interface timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 SPI interface timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Host Micro SPI pin list. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Flash SPI pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 SD/MMC SPI pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Host and auxiliary I2C interface pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 I2C interface timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 I2C1 interface device address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 I2C2 interface device address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 SDRAM Interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 SDRAM interface timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4/43
STA680
List of figures
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Functional data flow diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 STA680 block diagram (detailed) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Single channel application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Dual channel application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 LQFP pinout (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 LFBGA ballout (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Clock generation unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Power on timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 BBI waveforms and timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Serial audio interface waveforms and timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Three SPI timing diagrams and waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Timing diagrams and waveform for the two I2C interfaces . . . . . . . . . . . . . . . . . . . . . . . . . 33 Timing diagrams and waveform for the SDRAM interface . . . . . . . . . . . . . . . . . . . . . . . . . 35 LQFP144 (20x20mm) mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . 40 LFBGA 168 balls (12x12x1.4 mm) mechanical data and package dimensions . . . . . . . . . 41
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Description
STA680
1
Description
The STA680 from STMicroelectronics is a system on a chip designed for demodulating and decoding of HD Radio(a) signals. The STA680 is compliant with the IBiquity specification and extends the possibility to implement new and optional features and to manage additional services. The device combines it all into a single IC consisting of several hardware blocks and a programmable core to guarantee the proper level of flexibility, low current consumption and an optimized die size. The STA680 implements the entire signal processing chain of an HD Radio receiver.

The digital channel demodulation and decoding, including OFDM demodulation and error correction. Source decoding, consisting of audio and data decoding of the digital channel. The analog demodulator extracting the audio signal from the legacy analog AM/FM signal (can be implemented as an optional feature) The blending of the analog and digital audio signals
Figure 1 presents a functional diagram describing the data flow inside STA680 for HD Radio demodulating and decoding. The architecture consists of an effective and balanced hardware/software implementation, to pursue the best combination in terms of current consumption, system flexibility and device cost. Functional blocks which are standard, and computation intensive, are implemented using custom logic. Software implementation is more efficient for functional blocks where flexibility is needed. Such flexibility enables the STA680 to be ready for future evolution, and allows the implementation of specific and optional features. Figure 1.
I2S
Functional data flow diagram
Legacy AM/FM Samples
STA680
Blended Audio
Main BB Interface
Analog BBI1
Sample Rate Converter and Serial Interfaces
AM/FM Demodulation *
Blending *
Audio Samples
SRC SRC
Secondary BB Interface
I2S
Digital
Source Decoder Channel Decoder
DEMUX
Deinterleaver and Convolutional Decoding
SPI
HDC Decoder
I2C
BBI2
Digital
OFDM Demod
PSK/QAM Demod
* This features may be performed outside STA680 depending on the software configuration
SRC
Data Processing
DATA
AC00175
a. HD RadioTM technology manufactured under license from iBiquity Digital Corp. U.S. and Foreign Patents. HD RadioTM and the HD Radio logo are proprietary trademarks of iBiquity Digital Corp.
6/43
STA680
System overview
2
System overview
Figure 2 shows the partitioning of the HD Radio receiver system, composed by an AM/FM RF front-end, IF channel signal processor and the HD Radio decoder (STA680). Figure 2. STA680 block diagram (detailed)
8MB SDRAM 64 Mbit (4Mx16)
STA680
SDRAM Interface
Core System
Vectra LX Tensilica DSP
HiFi Tensilica Core
OTP
BBI 2 BBI 1
BaseBand Interface
AHB Bus
RF Tuner
(i.e. TDA7528)
AM/FM Baseband Tuner
(i.e. STA3004)
Tuner & Audio Interface
Clock Gen. Unit
Peripheral PLL
System PLL
Viterbi
AHB/APB Bridge
DMA
Boundary Scan JTAG
I2S
Audio Interface
Peripheral Bus
Slave Connection
LDO Crystal Oscillator I/O & Control Interface SPI Flash SPI SD/MMC SPI/I2C Micro i/f GPIO
Master Connection
Opt. Xtal 28.224 MHz
1MB SERIAL FLASH (bootable) 8 Mbit (1Mx8)
MMC,SD SDIO Cards
(4/8bit)
MAIN MICRO
The analog IF signal from the tuner front-end is digitized by a high-resolution sigma-delta A/D converter. A digital down-converter block, embedded into the IF channel signal processor, transforms the IF into a complex base-band signal. Its Bandwidth and sample rate have been adapted by filtering and decimation to match the specification of the HD Radio system. The complex base-band signal feed the HD Radio decoder (STA680) where the HD Radio stream is demodulated and decoded. The STA680 receives a digital base-band signal from the IF channel signal processor and returns the recovered audio and data services. STA680 can be configured to work with digital IF base-band inputs based on standard frontends. Front-ends must conform to HD Radio standards for filter bandwidth and linearity. The STA680 requires external serial Flash memory to boot but can also be configured to boot from a host controller on IIC or SPI interfaces. The FLASH memory Is issued for program code and configuration data storage. STA680 needs SDRAM for bulk data storage required during the IBOC signal processing.
7/43
System overview
STA680
2.1
HD Radio processing
The STA680 HD Radio Decoder does the processing of the IBOC signal. It receives a complex digital signal from an AM/FM IF channel signal processor. The native sample rate is 744.1875 kS/s for FM and 46.51171875 kS/s for AM. However, other input sample rates are acceptable because of the sample rate converter in the base-band Interface (BBI). These include: 650 kS/s, 675 kS/s, 882 kS/s and 912 kS/s. If a base-band signal is provided that is not at the native sample frequency of 744.1875 kHz it must be sample rate converted to this rate. Sample rate conversion hardware is provided on-chip to support this. This feature allows the STA680 to operate with various AM/FM front-ends. The STA680is then responsible for detection, acquisition, and demodulation of the IBOC signal. Such function is primarily implemented by the Vectra DSP core. The demodulated signal is then passes to the Hi-Fi processor, for decoding, audio blending and handling of data services. A digital 44.1 kHz decompressed audio is output via the Digital Audio Interface. The STA680 uses sophisticated algorithms to recover IBOC data even in the presence of signal impairments including fading and a variety of other interferences. To process the HD Radio stream STA680 requires a 4Mx16 external SDRAM (with up to 32Mx16 supported) for data storage.
2.2
Dual stream HD Radio processing
STA680 is capable to simultaneously demodulate two different HD Radio streams. This unique feature enables the device to decode an HD Radio audio stream, in parallel with any data service broadcasted by a different radio channel. The implementation of the dual stream HD Radio processing requires that two AM/FM RF tuners are connected to the STA680. In a single channel implementation a single RF tuner is used. In such configuration STA680 is able to demodulate at the same time both the audio and the data associated with the radio channel (i.e. 92.5 MHz or 102.5 MHz). This means that if the user sets the tuner 102.5 MHz, he or she can listed to FM2 audio and receive traffic information broadcasted on that channel. At the same time if the user tunes to another frequency (FM1), current traffic information will be lost. Figure 3. Single channel application
FM1 Audio
FM1 News
FM 1 FM1 Audio FM1 News 92.5 FM 2 FM2 Audio FM2 Traffic 102.5
MHz
OR
FM2 Audio
FM2 Traffic
Data received are bound to the selected Audio channel
8/43
STA680
System overview In a dual channels implementation STA680 can simultaneously demodulate audio and data associated to different radio channels. This means that in the example above it would be still possible to receive traffic information broadcasted on FM2 (102.5 MHz) while listening FM1 audio program broadcasted on 92.5 MHz Figure 4. Dual channel application
FM1 Audio
FM1 News
FM 1 FM1 Audio FM1 News 92.5
FM 2 FM2 Audio FM2 Traffic 102.5
MHz
FM1 Audio
OR
FM2 Traffic
FM2 Audio
OR
FM1 News
FM1 Audio
OR
FM2 Traffic
Audio and Data can belong to different channels
2.3
Additional processing
The HD Radio stream demodulation and decoding take up only part of the computation power and memories resources available on STA680. This makes it possible to use the spare resources to implement additional features. Depending on memory and computation power required by the additional features, it is possible to run them in parallel with the HD Radio stream decoding or in alternative, having all the hardware resources available for the additional features.
2.3.1
AM/FM processing
It is possible to implement legacy AM/FM processing in parallel with the HD Radio stream demodulation and decoding. Such solution is particularly suitable and appealing when the STA680 processor works jointly with an AM/FM RF front-end not incorporating the AM/FM demodulation.
2.3.2
Audio codec
STA680 can be used as a media processor to decode MP3/WMA audio stream. Thanks to the availability of the MMC and SD interface it is possible to reproduce an MP3 stream stored into any MMC or SD cards
9/43
System overview
STA680
2.3.3
Other
The spare computation power and memories are suitable to implement other specific algorithms or custom software application. For example sophisticated sound and audio processing could be implemented on the HD Radio decompressed audio. Audio output can be provided either in IIS master clock mode or in slave mode with the on-chip audio sample rate converter. Up to six audio channels may be provided in a standard configuration. Another possibility is to implement on the STA680 the handling of data services.
2.4
2.4.1
Overview of main functional blocks
Adjacent channel filter
This module performs time domain filtering specifically for IBOC system. It receives a complex base-band IBOC signal input from SRC module and pre-conditions the signal for subsequent modem processing. The module is a front end device.
2.4.2
HiFi2
The HiFi2 is a signal processing engine specifically designed to provide high quality 24-bit audio processing. The HiFi2 is also useful for advanced data applications such as storage and playback of received audio and conditional access processing. The HiFi2 leverages the Tensilica Xtensa LX engine with additional useful hardware capabilities such as:

Specialized instructions for 24-bit Audio MAC & stream coding Dual MAC (each supports 24x24 and 32x16 bit format) Huffman Encode / Decode and truncate functions Two way SIMD arithmetic and Boolean operations
2.4.3
Vectra
The Vectra LX is a powerful, configurable 32-bit RISC engine optimized for DSP with VLIW capabilities. The Vectra LX on board the STA680 includes eight MAC units, sixteen 160-bit vector operation registers, and a number of SIMD arithmetic instructions. Custom instructions in the Vectra are targeted for DSP applications such as filters and FFTs. The Vectra processor has been further configured with specific instructions for efficient performance on the HD Radio application.
2.4.4
DMA
A ten-channel DMA controller is attached to the AHB bus to allow the Vectra and HiFi2 processor cores to move large blocks of data efficiently. Certain channels are dedicated for use with certain hardware blocks because of hardware handshaking signals.
2.4.5
Hardware accelerator (VITERBI)
A complex convolutional Viterbi module is designed to fully comply with the HD Radio system. The module supports both K constant of 7 and 9, for IBOC digital FM and AM bands respectively.
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STA680
I/O description
3
I/O description
The STA680 has two package options to suit different application needs. The first option is a 20x20mm LQFP package with 144 pins while the second one is a 12x12mm LFBGA with 169 balls and 0.8mm pitch.
3.1
LQFP description
Figure 5 presents the pinout of the STA680 for the LQFP package option. Different colors have been used for I/O signals from different interfaces according to Table 2 reported in Section 3.3.
Figure 5.
LQFP pinout (top view)
GND_RAM_IO GND_RAM_IO GND_RAM_IO VDD_RAM_IO VDD_RAM_IO VDD_RAM_IO SDR_WE_N SDR_DQM1 111 SDR_DQM0 110
SDR_CS_N
SDR_RAS
SDR_CAS
SDR_CKE
SDR_BA1
SDR_BA0
SDR_A10
SDR_A11
SDR_A12
SDR_A3
SDR_A2
SDR_A1
SDR_A0
SDR_A4
SDR_A5
SDR_A6
SDR_A7
SDR_A8
SDR_A9
GND
GND
GND
144
143
142 141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
109
108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88
TESTMODE TRST_N TCK TMS TDI TDO RTS_GPIO0 VDD GND CTS_GPIO1 GND_GEN_IO VDD_GEN_IO TXD_GPIO2 RXD_GPIO3 RESET_N SPI1_SS0_N SPI1_SCK SPI1_MOSI VDD GND SPI1_MISO GND_GEN_IO VDD_GEN_IO IIC1_SCL IIC1_SDA BB2_Q GND VDD GND_GEN_IO VDD_GEN_IO BB2_I BB2_WS BB2_BCK BLEND BB1_Q VDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
GND
VDD
VDD
VDD
VDD SDR_D7 SDR_D6 SDR_D5 VDD_RAM_IO GND_RAM_IO SDR_D4 SDR_D3 SDR_D2 VDD GND SDR_D1 SDR_D0 SDR_D8 SDR_D9 VDD_RAM_IO GND_RAM_IO SDR_D10 SDR_D11 SDR_D12 VDD GND SDR_D13 SDR_D14 SDR_D15 SDR_FEED_CLK SDR_CLK_RAM3V3 VDD_RAM_IO_1V8 GND_RAM_IO_1V8 GND VDD SPI2_MISO SPI2_SCK SPI2_SS0_N SPI2_MOSI VDD_FSH_IO
Color legenda:
SDRAM Interface IIS Tuner Interfaces Flash/Card Interfaces Host Processor Interfaces GPIO & UART Interfaces IIS Audio Input Interface Audio Output Interfaces
87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70 GND
71 VDD
GND_PLL0_ANA
VDD_PLL0_ANA
GND_PLL_DIG
VDD_PLL_DIG
GND_OSC
ADAT3
ADAT2
ADAT
AUDIO_IN_ABCK
GND_GEN_IO
GND_GEN_IO
AUDIO_IN_ADAT
VDD_GEN_IO
VDD_GEN_IO
VDD_REG3V3
AUDIO_IN_AWS
VDD_REG1V8
GND_FSH_IO
CLK_IN
ABCK
GND
DAC256X
GND
BB1_I
SPDIF
VDD
GND
BB1_BCK
BB1_WS
AWS
VDD
VDD_OSC
OSC_IN
OSC_OUT
72
AC00504
11/43
I/O description
STA680
3.2
LFBGA description
Figure 6 presents the ballout of the STA680 for the LFBGA package option. Different colors have been used for I/O signals from different interfaces according to Table 2 reported in Section 3.3.
Figure 6.
1
LFBGA ballout (top view)
2 3 4 5 6 7 8 9 10 11 12 13 14
A
GPIO6
BB2_BCK
BB2_I
GND_IO_GEN
IIC1_SDA
SPI1_MISO
SPI1_SCK
RESET_N
TXD_GPIO2
RTS_GPIO0 VDD_GEN_IO TESTMODE
B
GPIO5
BB1_Q
BLEND
BB2_WS
GND_IO_GEN
BB2_Q
IIC1_SCL
SPI1_MOSI
SPI1_SS0_N
RXD_GPIO3
CTS_GPIO1 VDD_GEN_IO
SDR_A3
TRST_N
C
BB1_WS
BB1_I
ADAT2
IIC2_SDA
GPIO7
IIC2_SCL
IIC1_DA
SPI3_MOSI
SPI3_MISO
SPI3_SCK
TDI
TCK
SDR_A1
SDR_A2
D
VDD_GEN_IO VDD_GEN_IO
BB1_BCK
IIC2_DA
VDD
VDD
SPI3_SS_N
GPIO4
TDO
TMS
SDR_A10
SDR_A0
E
AUDIO_IN_ ABCK
SPDIF
ADAT3
VDD_PLL_DIG
VDD
MODEOP_FSH
SDR_BA0
SDR_BA1
F
AUDIO_IN_ ADAT
AUDIO_IN_ AWS
GND_PLL_ DIG
GND_PLL_ DIG
GND
GND
GND
GND
VDD
MODEOP_GEN SDR_RAS_N
SDR_CS_N
G
AWS
ADAT
DAC256X
GND
GND
GND
GND
SDR_CAS_N
SDR_WE_N VDD_RAM_IO
H
GND_IO_GEN GND_IO_GEN
ABCK
GND
GND
GND
GND
SDR_A4
SDR_A5
GND_RAM_IO
J
VDD_OSC
GND_OSC
GND_PLL1_ GND_PLL0_ ANA ANA
GND
GND
GND
GND
VDD
VDD
SDR_A7
SDR_A6
K
OSC_OUT
CLK_IN
VDD
VDD_REG3V3
VDD
VDD
SDR_A9
SDR_A8
L
OSC_IN
GND_OSC
VDD
VDD_REG3V3 VDD_FSH_IO GND_FSH_IO
VDD_RAM_ IO_1V8
GND_RAM_ GND_RAM_IO GND_RAM_IO IO_1V8
SDR_A12
SDR_A11
M
VDD_PLL1_ ANA
VDD_PLL0_ ANA
SPI2_SS1_N SPI2_SS2_N
SPI2_SS3_N
SDR_CLK_ RAM1V8
SDR_D13
SDR_D10
VDD_RAM_IO VDD_RAM_IO GND_RAM_IO GND_RAM_IO SDR_DQM1
SDR_CKE
N
VDD_REG1V8 VDD_REG1V8 SPI2_MOSI
SPI2_SCK
SDR_CLK_ RAM3V3
SDR_D15
SDR_D12
SDR_D9
SDR_D0
SDR_D2
SDR_D4
SDR_D6
SDR_DQM0
P
SPI2_SS0_N
SPI2_MISO
SDR_FEED_ CLK
SDR_D14
SDR_D11
SDR_D8
SDR_D1
SDR_D3
SDR_D5
SDR_D7
AC00707
Color legenda:
Ball unused
Ball not present
SDRAM Interface
IIS Tuner Interfaces
Flash/Card Interfaces
Host Processor Interfaces
GPIO & UART Interfaces
IIS Audio Input Interface
Audio Output Interfaces
12/43
STA680
I/O description
3.3
Pin list
The Table 2 briefly describes the main function and characteristics of the STA680 I/O signals in normal operation mode.
Table 2.
Pin # Test 1
Pins description
Ball # Signal name Type Electrical Supply group Description
A13
TESTMODE
input
1.8 V or 3.3 V
Generic IO Factory test mode Supply
Standard 1149.1 JTAG interface
2 3 4 5 6 B14 C12 D12 C11 D11 TRST_N TCK TMS TDI TDO input input input input input 1.8 V or 3.3 V 1.8 V or 3.3 V 1.8 V or 3.3 V 1.8 V or 3.3 V 1.8 V or 3.3 V Generic IO JTAG active-low test reset Supply Generic IO JTAG test clock Supply Generic IO JTAG test mode state Supply Generic IO JTAG test data in Supply Generic IO JTAG test data out Supply
GPIO & UART interfaces
7 10 13 14 Not bonded Not bonded Not bonded Not bonded Reset 15 A9 RESET_N input 1.8 V or 3.3 V Generic IO Device active-low reset Supply A11 B11 A10 B10 D10 B1 B2 C5 RTS_GPIO0 CTS_GPIO1 TXD_GPIO2 RXD_GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 in/out in/out in/out in/out in/out in/out in/out in/out 1.8 V or 3.3 V 1.8 V or 3.3 V 1.8 V or 3.3 V 1.8 V or 3.3 V 1.8 V or 3.3 V 1.8 V or 3.3 V 1.8 V or 3.3 V 1.8 V or 3.3 V Generic IO UART ready to send /GPIO bit 0 Supply Generic IO UART clear to send /GPIO bit 1 Supply Generic IO UART transmit data /GPIO bit 2 Supply Generic IO UART receive data /GPIO bit 3 Supply Generic IO GPIO bit 4 Supply Generic IO GPIO bit 5 Supply Generic IO GPIO bit 6 Supply Generic IO GPIO bit 7 Supply
13/43
I/O description Table 2.
Pin #
STA680
Pins description (continued)
Ball # Signal name Type Electrical Supply group Description
Host processor interfaces 16 17 18 21 24 25 Not bonded Not bonded Not bonded Not bonded B9 A8 B8 A7 B7 A6 C7 C6 C4 D4 SPI1_SS0_N SPI1_SCK SPI1_MOSI SPI1_MISO IIC1_SCL IIC1_SDA IIC1_DA IIC2_SCL IIC2_SDA IIC2_DA input input input 1.8 V or 3.3 V 1.8 V or 3.3 V 1.8 V or 3.3 V Generic IO SPI interface 1 active-low slave Supply select Generic IO SPI interface 1 serial clock Supply Generic IO SPI interface 1 serial data master out/slave in Supply Generic IO SPI interface 1 serial data master Supply in/slave out Generic IO Supply Generic IO Supply IIC interface 1 serial clock line IIC interface 1 serial data line
output 1.8 V or 3.3 V in/out in/out in/out in/out in/out in/out 1.8 V or 3.3 V 1.8 V or 3.3 V 1.8 V or 3.3 V 1.8 V or 3.3 V 1.8 V or 3.3 V 1.8 V or 3.3 V
Generic IO IIC interface 1 data acknowledged Supply Generic IO Supply Generic IO Supply IIC interface 2 serial clock line IIC interface 2 serial data line
Generic IO IIC interface 2 data acknowledged Supply
I2S tuner interfaces 40 35 41 42 31 26 32 33 C2 B2 C1 D3 A4 B6 B4 A3 BB1_I BB1_Q BB1_WS BB1_BCK BB2_I BB2_Q BB2_WS BB2_BCK input input input input input input input input 1.8 V or 3.3 V 1.8 V or 3.3 V 1.8 V or 3.3 V 1.8 V or 3.3 V 1.8 V or 3.3 V 1.8 V or 3.3 V 1.8 V or 3.3 V 1.8 V or 3.3 V Generic IO Primary base-band interface Supply serial I data Generic IO Primary base-band interface Supply serial Q data Generic IO Primary base-band interface word strobe Supply Generic IO Primary base-band interface bit Supply clock Generic IO Secondary base-band interface Supply serial I data Generic IO Secondary base-band interface Supply serial Q data Generic IO Secondary base-band interface Supply word strobe Generic IO Secondary base-band interface Supply bit clock
14/43
STA680 Table 2.
Pin #
I/O description Pins description (continued)
Ball # Signal name Type Electrical Supply group Description
I2S audio input interface 45 44 50 F2 E1 F1 AUDIO_IN_AWS AUDIO_IN_ABCK AUDIO_IN_ADAT input input input 1.8 V or 3.3 V 1.8 V or 3.3 V 1.8 V or 3.3 V Generic IO Digital audio input word strobe Supply Generic IO Digital audio input bit clock Supply Generic IO Digital audio input serial data Supply
Audio output interfaces 55 56 54 53 52 43 34 51 G1 H3 G2 C3 E3 E2 B3 G3 AWS ABCK ADAT ADAT2 ADAT3 SPDIF BLEND DAC256X in/out in/out 1.8 V or 3.3 V 1.8 V or 3.3 V Generic IO Digital audio output word strobe Supply Generic IO Digital audio output clock Supply Generic IO Digital audio output serial data Supply Generic IO Digital audio output serial data Supply channel 2 Generic IO Digital audio output serial data Supply channel 3 Generic IO Digital audio output in SPDIF Supply format Generic IO Digital audio output blend output Supply Generic IO Digital audio output Supply oversupplying clock (256 x Fs)
output 1.8 V or 3.3 V output 1.8 V or 3.3 V output 1.8 V or 3.3 V output 1.8 V or 3.3 V output 1.8 V or 3.3 V output 1.8 V or 3.3 V
Clock and oscillator
57 66 67 K2 L1 L2 CLK_IN OSC_IN OSC_OUT input analo g analo g 1.8 V or 3.3 V 1.8 V 1.8 V Generic IO Reference digital clock Supply Osc Supply Osc Supply 28,224MHz crystal in or digital clock input Crystal output
SPI Flash interface 77 74 75 Not bonded P4 N3 P3 M3 SPI2_MISO SPI2_MOSI SPI2_SS0_N SPI2_SS1_N input 1.8 V or 3.3 V Flash IO Supply Flash IO Supply Flash IO Supply Flash IO Supply SPI interface 2 serial data master in/slave out SPI interface 2 serial data master out/slave in SPI interface 2 active-low slave select 0
output 1.8 V or 3.3 V output 1.8 V or 3.3 V output 1.8 V or 3.3 V
SPI interface 2 active-low slave
select 1
15/43
I/O description Table 2.
Pin # Not bonded Not bonded 76
STA680
Pins description (continued)
Ball # M4 M5 N4 Signal name SPI2_SS2_N SPI2_SS3_N SPI2_SCK Type Electrical Supply group Flash IO Supply Flash IO Supply Flash IO Supply select 2 Description
output 1.8 V or 3.3 V output 1.8 V or 3.3 V output 1.8 V or 3.3 V
SPI interface 2 active-low slave SPI interface 2 active-low slave
select 3
SPI interface 2 serial clock
SPI SD/MMC interface Not bonded Not bonded Not bonded Not bonded C9 C8 D9 C10 SPI3_MISO SPI3_MOSI SPI3_SS_N SPI3_SCK input 1.8 V or 3.3 V Generic IO SPI interface 3 serial data master Supply in/slave out Generic IO SPI interface 3 serial data master Supply out/slave in Generic IO SPI interface 3 active-low slave select Supply Generic IO SPI interface 3 serial clock Supply
output 1.8 V or 3.3 V output 1.8 V or 3.3 V output 1.8 V or 3.3 V
SDRAM interface 83 82 Not bonded 96 97 100 101 102 105 106 107 95 94 P5 N5 M6 N9 P9 N10 P10 N11 P11 N12 P12 P8 P9 SDR_FEED_CLK input 3.3 V 3.3 V 1.8 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V SDRAM IO Feedback clock farmsteads Supply interface SDRAM IO Clock distrain for 3.3 V interface Supply SDRAM Supply Clock to SDRAM for 1.8 V interface
SDR_CLK_RAM3.3 V output SDR_CLK_RAM1.8 V output SDR_D0 SDR_D1 SDR_D2 SDR_D3 SDR_D4 SDR_D5 SDR_D6 SDR_D7 SDR_D8 SDR_D9 in/out in/out in/out in/out in/out in/out in/out in/out in/out in/out
SDRAM IO SDRAM bidirectional data bit 0 Supply SDRAM IO SDRAM bidirectional data bit 1 Supply SDRAM IO SDRAM bidirectional data bit 2 Supply SDRAM IO SDRAM bidirectional data bit 3 Supply SDRAM IO SDRAM bidirectional data bit 4 Supply SDRAM IO SDRAM bidirectional data bit 5 Supply SDRAM IO SDRAM bidirectional data bit 6 Supply SDRAM IO SDRAM bidirectional data bit 7 Supply SDRAM IO SDRAM bidirectional data bit 8 Supply SDRAM IO SDRAM bidirectional data bit 9 Supply
16/43
STA680 Table 2.
Pin # 91 90 89 86 85 84 110 111 127 128 129 112 132 133 134 138 139 140 141 126 123
I/O description Pins description (continued)
Ball # M8 P7 N7 M7 P6 N6 N13 M13 G13 G12 F13 M14 F14 E13 E14 D14 C13 C14 B13 H12 H13 Signal name SDR_D10 SDR_D11 SDR_D12 SDR_D13 SDR_D14 SDR_D15 SDR_DQM0 SDR_DQM1 SDR_WE_N SDR_CAS_N SDR_RAS_N SDR_CKE SDR_CS_N SDR_BA0 SDR_BA1 SDR_A0 SDR_A1 SDR_A2 SDR_A3 SDR_A4 SDR_A5 Type in/out in/out in/out in/out in/out in/out output output output output output output output output output output output output output output output Electrical 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V Supply group Description
SDRAM IO SDRAM bidirectional data bit 10 Supply SDRAM IO SDRAM bidirectional data bit 11 Supply SDRAM IO SDRAM bidirectional data bit 12 Supply SDRAM IO SDRAM bidirectional data bit 13 Supply SDRAM IO SDRAM bidirectional data bit 14 Supply SDRAM IO SDRAM bidirectional data bit 15 Supply SDRAM IO low-byte data input/output mask Supply SDRAM IO high-byte data input/output mask Supply SDRAM IO Active-low write enable Supply SDRAM IO Active-low column address strobe Supply SDRAM IO Active-low row address strobe Supply SDRAM IO Clock enable Supply SDRAM IO Active-low chip select Supply SDRAM IO Bank select address 0 Supply SDRAM IO Bank select address 1 Supply SDRAM IO Address bit 0 toSDRAM Supply SDRAM IO Address bit 1 toSDRAM Supply SDRAM IO Address bit 2 toSDRAM Supply SDRAM IO Address bit 3 toSDRAM Supply SDRAM IO Address bit 4 toSDRAM Supply SDRAM IO Address bit 5 toSDRAM Supply
17/43
I/O description Table 2.
Pin # 122 121 118 117 137 116 115 Supplies
STA680
Pins description (continued)
Ball # J14 J13 K14 K13 D13 L14 L13 Signal name SDR_A6 SDR_A7 SDR_A8 SDR_A9 SDR_A10 SDR_A11 SDR_A12 Type output output output output output output output Electrical 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V Supply group Description
SDRAM IO Address bit 6 toSDRAM Supply SDRAM IO Address bit 7 toSDRAM Supply SDRAM IO Address bit 8 toSDRAM Supply SDRAM IO Address bit 10 toSDRAM Supply SDRAM IO Address bit 10 toSDRAM Supply SDRAM IO Address bit 11 toSDRAM Supply SDRAM IO Address bit 12 toSDRAM Supply
Not bonded
F12
MODEOP_GEN
input
3.3 V
Define the operating voltage of the "Generic I/O" supply group. If SDRAM IO tied low the I/Os work at 1.8V else Supply they work at 3.3V. Default value is 3.3V. Define the operating voltage of the "Flash I/O" supply group. If SDRAM IO tied low the I/Os work at 1.8V else Supply they work at 3.3V. Default value is 3.3V.
Not bonded
E12
MODEOP_FSH
input
3.3 V
8, 19, D5, D6, 28, 36, E11, 46, 59, F11, 71, 78, J11, VDD 88, 99, J12, 108, K3, 119, K11, 130, 143 K12, L3 9, 20, 27, 37, 47, 58, 70, 79, 87, 98, 109, 120, 131, 142 11, 22, 27, 38, 48 F6, F7, F8, F9, G6, G7, G8, G9, GND H6, H7, H8, H9, J6, J7, J8, J9 A5, B5, GND_GEN_IO H1, H2
power
1.2 V
Core Supply
Power supply for core logic
power
-
Core Supply
Ground for core logic
power
-
Generic IO Generic I/Os ground Supply
18/43
STA680 Table 2.
Pin # 12, 23, 30, 39, 49 72 73
I/O description Pins description (continued)
Ball # Signal name Type Electrical Supply group Description
A12, B12, VDD_GEN_IO D1, D2 L6 L5 H14, L11, L12, M11, M12 G14, M9, M10 GND_FSH_IO VDD_FSH_IO
power 1.8 V or 3.3 V
Generic IO Generic I/Os power supply Supply Flash IO Supply Flash IO Supply
power
-
Ground for Flash Interface I/Os Power supply for Flash Inteface
I/Os
power 1.8 V or 3.3 V
92, 103, 114, 125, 136 93, 104, 113, 124, 135
GND_RAM_IO
power
-
SDRAM IO Ground forSDRAM Interface I/Os Supply
VDD_RAM_IO
power
3.3 V
SDRAM IO Power supply forSDRAM Supply Interface I/Os 1.8 V SDRAM Clock Supply 1.8 V SDRAM Clock Supply
81
L9
VDD_RAM_IO_1.8 V
power
1.8 V
Power supply forSDRAM clock pad at 1.8 Volt
80
L10
GND_RAM_IO_1.8 V power
-
Ground forSDRAM clock pad at
1.8 volt
60 61
F3, F4 E4
GND_PLL_DIG VDD_PLL_DIG
power power
1.2 V
PLL Digital Ground for PLL digital part Supply PLL Digital Power supply for PLL digital part Supply PLL Analog Supply PLL Analog Supply PLL Analog Supply PLL Analog Supply Osc Supply Osc Supply
62
J4
GND_PLL0_ANA(1)
power
-
Ground for PLL0 analog part
62
J3
GND_PLL1_ANA(1)
power
-
Ground for PLL1 analog part Power supply for PLL0 analog
part
63
M2
VDD_PLL0_ANA(2)
power
1.8 V
63
M1
VDD_PLL1_ANA(2)
power
1.8 V
Power supply for PLL1 analog
part
64 65
J2, L2 J1
GND_OSC VDD_OSC
power power
1.8 V
Ground for oscillator core Power supply for oscillator core
19/43
I/O description Table 2.
Pin # 68 69
STA680
Pins description (continued)
Ball # K4, L4 Signal name VDD_REG3.3 V Type power power Electrical 3.3 V 1.8 V Supply group LDO Supply LDO Supply Description Input power supply for voltage regulator at 3.3 Volt Output power supply from voltage regulator at 1.8 Volt
N1, N2 VDD_REG1.8 V
3.4
I/Os supply groups
The STA680 I/O signals are arranged into three different supply groups: Generic IO supply, Flash IO supply and SDRAM IO supply group (see Table 2). In the LQFP package option all three groups must be supplied with 3.3 V. In the LFBGA package the three supply groups can independently operate at 3.3 V or 1.8 V.

The SDRAM_IO supply group must always be supplied at 3.3 V. The MODEOP_GEN pin selects the operating voltage of the Generic_IO supply group. If the it is shorted to ground then all the I/O signals belonging to the Generic_IO supply group will work at 1.8 V; if the MODEOP_GEN pin is left floating or it is tied high (3.3 V) all the group I/Os will operate at 3.3 V. The MODEOP_FSH pin selects the operating voltage of the Flash_IO supply group. If the it is shorted to ground then all the I/O signals belonging to the Flash_IO supply group will work at 1.8 V; if the MODEOP_FSH pin is left floating or it is tied high (3.3 V) the Flash Interface I/Os will operate at 3.3 V.
20/43
STA680
Operation and general remarks
4
4.1
Operation and general remarks
Clock schemes
The STA680 needs an external clock source to feed the internal Phase Locked Loops (PLLs) to generate all the frequency needed by its cores and peripherals. This reference clock may be supplied in several ways thus offering flexibility in the development of the final application:

The reference clock may be supplied through the use of an external crystal or as a digital signal coming from an external IC. The reference clock may have different frequencies and can be fed to the STA680 through different input pins.
The selection of the clock input mode is performed during the power-on phase of the device by latching the value of the pins ADAT3, BLEND and DAC256X on the rising edge of the RESET_N signal (see Chapter 4.2); this value shall be selected according to Table 3. Table 3. Reference clock configuration
Clock type Crystal Digital Digital Digital Digital Digital Digital Digital Input pin OSC_IN OSC_IN or CLK_IN OSC_IN or CLK_IN
(2) (2)
[ADAT3, BLEND, DAC256X] [0,0,0] (1) [0,0,1] [0,1,0] [0,1,1] [1,0,0] [1,0,1] [1,1,0] [1,1,1]
1. Default setting.
Clock frequency (MHz) 28.224 23.3472 36.48 2.9184 10.4 10.8 14.112 2.9184
OSC_IN or CLK_IN (2) BB1_BCK BB1_BCK BB1_BCK AUDIO_IN_ABCK
2. When using OSC_IN pin to input the reference clock the CLK_IN pin must be connected to ground and vice versa.
21/43
Operation and general remarks Figure 7 shows a simplified version of the internal clock generation unit. Figure 7. Clock generation unit
STA680
Core Clock PLL BB1_BCK AUDIO_IN_ABCK CLK_IN OSCI_IN OSCI_OUT Internal Oscillator OSC_EN Encoder CLK_SEL
Clock to Cores
Peripheral Clock PLL
Clock to Peripherals
PLL Settings
DAC256X
BLEND
Some remarks on the choice of the clock input pin must be done:

OSC_IN is always a 1.8 V input pin. CLK_IN, BB1_BCK and AUDIO_IN_ABCK are 3.3 V pins when the LQFP package is selected while they can be configured as a 3.3 V or 1.8 V pins if the LFBGA is chosen (see Chapter 3.4) When the clock is fed through CLK_IN pin, the OSC_IN pin must be connected to ground. Similarly if the clock is fed using CLK_IN pin then the OSC_IN pin must be connected to ground. The BB1_BCK pin is the bit clock of the digital interface to the base-band Tuner, so to fed the reference clock through this pin the selected clock frequency must be chosen accordingly to the Primary base-band Interface settings (see Chapter 5.2): - - - 10.4 MHz = 16 * 2 * 650 kHz BBI set to 650 Ksample/s 10.8 MHz = 16 * 2 * 675 kHz BBI set to 675 Ksample/s 14.112 MHz = 16 * 2 * 882 kHz BBI set to 882 Ksample/s
ADAT3
AC00712
The AUDIO_IN_ABCK is the bit clock of the digital audio input interface to the Tuner. When this pin is selected as clock source the STA680 Input Serial Audio Interface (see Chapter 5.3.2) must be set according to following specification: - - - Slave mode Input sample rate = 45.6 kHz Word length = 32 bit
With this settings the reference clock frequency is 2.9184 MHz = 32 * 2 * 45.6 kHz.
22/43
STA680
Operation and general remarks
4.2
Power on
This chapter describes the power-on procedure for the cold start (cold start means that the device is completely disconnected from the power supply before being turned on). Figure 8 and Table 4 show the timing for the power up sequence of the cold start. Figure 8. Power on timing
Core Supply (1.2V) I/Os Supply (3.3V or 1.8 V) LDO Input Supply (3.3V) LDO Output Supply (1.8V)
TRamp - up TDC1V8
OSC_IN
TOSC
OSC_OUT
TRST
RESET_N
ADAT ADAT2
set for jtag /tap config . TCFG
ADAT3 BLEND DAC256X
set for clock
config .
Core Clock
AC00708
primary boot
Min @ 2.9184MHz Max @ 38.48MHz
secondary boot
@ 28.224MHz
functional mode
max @ 166MHz
Table 4.
Symbol Tramp-up TDC1V8 TOSC TRST TCFG
Power on timing parameters
Parameter External supply ramp-up time DC1V8 regulator start-up time Oscillator start-up time Reset release time Setup of clock/jtag configuration Min TBD 300 0.18 1.1 0.1 Max Unit s s ms s s
4.2.1
Power supply ramp up phase
All power supplies must be ramped-up to their specified levels within the time TRamp-up, set by the external power supply circuit on the board. The ramp up phase of each power domain should start at the same time. The RESET_N pin must be kept low since the beginning. For normal applications, the TESTMODE pin (Factory test mode enable, see Table 2) must be connected to ground.
23/43
Operation and general remarks
STA680
4.2.2
Oscillator setting time
Once the power supply has reached the operating level, the internal voltage regulator gets functional after TDC1V8 = 300 s (see Table 4) and starts supplying the 1.8 V voltage to internal IPs such as PLLs and Crystal Oscillator. The PLL is powered up but not yet functioning since the internal logic keeps it in bypass mode until a stable clock is available and STA680 has entered the secondary boot phase. As shown in Figure 8, if an external crystal is connected to the internal oscillator this will output a correct waveform after TOSC = 0.18 ms (seeTable 4). At this time, if no crystal is used, a digital clock must be supplied according to the instructions detailed in Section 4.1. Either if an external crystal is used or the reference clock is provided through a digital source, the RESET_N pin must be kept low for an additional TRST = 1.1 s. As described in Section 4.1 the internal clock configuration is defined latching on the rising edge of the RESET_N signal the value of the pins ADAT3, BLEND and DAC256X; the value of this three signals must be stable at least TCFG = 0.1 s before the leading edge of the RESET_N signal.
4.2.3
Boot sequence
Once the RESET_N signal has been released and the power up sequence correctly performed, the STA680 enters the boot procedure, which consists of two phases consisting of device setup and application authentication and download. During the first phase the STA680 executes the on-chip primary boot code contained in the 32 kilobyte Boot ROM. The primary boot synchronizes the internal cores, initializes the SPI and IIC interfaces and automatically selects the secondary boot code source by searching a pre-defined pattern into UART1, Flash, SPI1, IIC1 and IIC2. Once the device on which the secondary boot resides has been found, following tasks are performed: the code is authenticated, the SDRAM is initialized and the secondary boot code is downloaded into it. The downloading speed depends on the device reference clock frequency even if this parameter does not have a big impact on the overall boot time since the dimension of this part of the code is small. During the second phase of the boot procedure to achieve acceptable boot time the STA680 performs PLLs setup and takes the internal clock frequency to 28.224 MHz (see Figure 8) then downloads and validates the application code from the external Flash memory. This last task ends the boot procedure.
4.2.4
Normal operation mode
After the execution of the boot code, the device enters the normal operation mode by jumping to the main program loop.
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STA680
Digital I/O and memory interfaces
5
5.1
Digital I/O and memory interfaces
Interfaces: LQFP vs. LFBGA
The STA680 interface set depends on the package option selected, the LFBGA giving the maximum flexibility where the LQFP package has a slightly smaller set of interfaces, due to its smaller pin count. The differences between the two package options are detailed in Table 5. Table 5. Interface list
Interface name Base-band interface 1 Base-band interface 2 (data only) I
2S
Direction I I I O I/O I/O I/O I/O I/O I/O I/O O I/O I/O I/O
LQFP x x x x
LFBGA
audio input audio output (six channels)
I2S
I2C primary interface (Micro) I
2C
secondary Interface
SPI micro interface SPI Flash interface (single chip select) SPI Flash interface extension (up to 4 chip select) SPI SD/MMC SDRAM interface S/PDIF interface UART interface 4 GPIO lines JTAG test interface (boundary scan only)
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5.2
Tuner interface
The STA680 provides two digital base-band interfaces, named BBI1 and BBI2, through which the demodulated IBOC signals can enter the HD Radio decoder. The base-band Tuner accepts the analog signal from the RF Tuner, samples it, performs down conversion and filtering, and sends the zero-IF signal across a base-band interface (BBI) to the STA680. Using two interfaces the STA680 is able to decode two channels at the same time, allowing the implementation of features such as the background scanning of HD Radio channels in search of traffic or weather information. The BBI consists of four-wires, 16 bit wide I and Q data and two clocks. MSB is always transmitted first. All signals are assumed to be zero-if. The native rate for FM is 744.1875 kS/s and for AM it is 46.51171875 kS/s. Sample rates of 650 kS/s, 675 kS/s, 882 kS/s and 912 kS/s are acceptable via the use of a sample rate converter. BBI2 is similar to BBI1 except BBI2 doesn't have center filter so it is intended to be used for digital modulated signal only. For pin description refers to the Table 5. Table 6. Base-band interfaces pin list
Designation Secondary base band interface word strobe Primary base-band interface bit clock Primary base-band interface serial I data Primary base-band interface serial Q data Secondary base-band interface word strobe Secondary base-band interface bit clock Secondary base-band interface serial I data Secondary base-band interface serial Q data Type I I I I I I I I Drive -
Pin name BB1_WS BB1_BCK BB1_I BB1_Q BB2_WS BB2_BCK BB2_I BB2_Q
The data stream of the base-band interface varies depending on the mode selected. Split mode splits I and Q data onto the BB1_I and BB1_Q pins, respectively. The rising and falling edges of BB1_WS mark the beginning of each I and Q pair. Multiplexed mode places the I and Q data onto the BB1_I data pin. The falling edge of BB1_WS marks the start of the I data and the rising edge marks the start of Q data. AFE mode uses a single clock pulse on BB1_WS to indicate the start of I data followed by Q data using the BB1_I pin only. Figure 9 show signals waveform for the three modes.
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STA680 Figure 9. BBI waveforms and timings
2/Fws BBx_WS Sample N (I and Q) 1/Fbck,split BBx_BCK Ts BBx_I I15 I14 I13 I12 Th I11 ... ... I4 I3 I2 I1 I0 I15 I14 I13 I12
Digital I/O and memory interfaces
Sample N+1 (I and Q)
I11 ...
...
I4
I3
I2
I1
I0
BBx_Q
Q15 Q14 Q13 Q12 Q11 ...
...
Q4
Q3
Q2
Q1
Q0
Q15 Q14 Q13 Q12 Q11 ...
...
Q4
Q3
Q2
Q1
Q0
Split Mode
1/Fws BBx_WS Sample N (I) 1/Fbck,mux BBx_BCK Ts BBx_I I15 I14 I13 I12 Th I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0 Q15 Q14 Q13 Q12 Q11 Q10 Q9 Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Sample N (Q)
Multiplexed Mode
1/Fws BBx_WS Sample N (I) 1/Fbck,afe BBx_BCK Ts BBx_I I15 I14 I13 I12 Th I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0 Q15 Q14 Q13 Q12 Q11 ... ... Q4 Q3 Q2 Q1 Q0 Sample N (Q)
AFE Mode
AC00713
In Table 7 are reported the timing values for the BB interface. Table 7.
Symbol Fws Fbck,split Fbck,mux Fbck,afe Th Ts
BBI timing values
Parameter Word strobe Bit clock in split mode Bit clock in multiplexed mode Bit clock in AFE mode Data hold time Data setup time Condition 650 16 x Fws 32 x Fws 32 x Fws 4 8 675 Working rate 744.188 882 66 32 x Fws 66 912 Unit kHz MHz MHz MHz ns ns
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5.3
Audio interface (AIF)
The AIF (Audio Interface) is used for the communication with external digital signal sources and receivers. The main AIF features are:

1 Input SAI interface. 3 Output SAI interface. 1 S/PDIF transmitter. Audio Sample Rate Converter (ASRC). I/O sample rates: 44.1 kHz, 45.6 kHz, 48 kHz.
The AIF includes 1 Input SAI interface, 3 Output SAI interface and 1 S/PDIF (industry standard) transmitter. The receivers and transmitters can be used either in master-mode, running with the STA680 internal audio frequency of 44.1 kHz or in slave mode running with a frequency determined by the external device. In slave mode, in order to adapt the external data rate to the internal audio data rate, it is possible to use an internal Audio Sample Rate Converter (ASRC, see Chapter 5.3.4). Table 8. AIF pin list
Designation Digital audio input word strobe Digital audio input bit clock Digital audio input serial data Digital audio output word strobe Digital audio output clock Digital audio output serial data Digital audio output serial data channel 2 Digital audio output serial data channel 3 Digital audio output oversampling clock (256 x Fs) Digital audio output in SPDIF format Digital audio output blend output Type I I I I/O I/O O O O O O O Drive 4mA 4mA 4mA 4mA 4mA 4mA 4mA 4mA
Pin name AUDIO_IN_AWS AUDIO_IN_ABCK AUDIO_IN_ADAT AWS ABCK ADAT ADAT2 ADAT3 DAC256X SPDIF BLEND
5.3.1
Output serial audio interface (SAI)
The output serial audio interface is used to send decoded audio samples from the HD Radio Decoder to an external IC for audio processing, or directly to a digital power amplifier. The output SAI is an I2S interface which provides audio samples in stereo at a 44,1 kS/s sample rate. Other sample rates may be provided by means of the internal ASRC (see Chapter 5.3.4). The output SAI interface shares the word strobe and the bit clock signal with three data output signals in order to support up to a total of 3 stereo channels of audio output. For interfacing the STA680 to an external DAC an oversampling clock whose frequency is 256 times the sampling frequency is provided. For pin description refers to Table 8. The output SAI supports a 32x or 64x bit clock. The 32x clock mode shifts out serial data with no padding. The 64x clock mode shifts out the 16-bit audio data first followed by 16 bits of zero padding. Figure 10 shows timing diagrams for the supported modes.
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STA680 Figure 10. Serial audio interface waveforms and timings
1/Faws
Digital I/O and memory interfaces
AWS
LEFT 1/Fabck,16
RIGHT
ABCK
ADAT
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1 D0 D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
32X Mode (16 - bit data)
1/Faws
AWS
LEFT 1/Fabck,32
RIGHT
ABCK Ts ADAT D15 D14 D13 ... ... D3 D2 D1 Th D0 0 0 0 ... ... 0 0 D15 D14 D13 D3 D2 D1 D0 0 0 0 0 0
64X Mode (32 - bit data)
AC00717
In Table 9 are reported the timing values for the output SAI interface. Table 9.
Symbol Faws Fabck,16 Fabck,32 Th Ts
Serial audio interface timing values
Parameter Word strobe Bit clock for 16-bit data Bit clock for 32-bit data Data hold time Data setup time Condition Working rate 44.1 10 Hz 45.6 15 Hz 32 x Faws 64 x Faws 5 20 48 15 Hz Unit kHz MHz MHz ns ns
5.3.2
Input serial audio interface
The input serial audio interface is used to receive the legacy AM/FM demodulated samples from an external AM/FM Tuner for blending purpose. The input SAI is an I2S interface which accepts 16 bit audio samples in stereo at a 44,100 S/s sample rate. Other sample rates may be supported by means of the internal ASRC. For pin description refers to Table 8. The input SAI supports a 32x or 64x bit clock. The 32x clock mode shifts out serial data with no padding. The 64x clock mode shifts out the 16-bit audio data first followed by 16 bits of zero padding. Figure 10 shows timing diagrams for the supported modes.
5.3.3
S/PDIF interface
The S/PDIF Interface is an output only. It is compliant to the standard IEC 958 type II. For pin description refers to Table 8.
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5.3.4
Audio sample rate converter (ASRC)
The STA680 supports various external host audio interfaces. The audio sample rate converter is designed to interface the audio output to systems with local master audio clock sources. Output sample rates of 44,100 ( 10 Hz), 45,600 ( 15 Hz) and 48,000 ( 15 Hz) are acceptable. Total harmonic distortion plus noise (THD+N) at 1 kHz is greater than 85 dB down (0.0056%). One stereo channel (i.e. single ADAT line) either from the input SAI or from the output SAI can be used with the audio sample rate converter. In applications where the STA680 supplies the master clock to the audio D/A converter, the ASRC will be bypassed.
5.4
Serial peripheral interfaces (SPI)
The STA680 provides three serial peripheral interfaces, each one intended for a different and specific purpose:
SPI1 - The first SPI is intended for communicating with the Host Microcontroller. Alternatively to this purpose can be also the Host Micro I2C Interface (see Chapter 5.4.1) SPI2 - The second SPI has been taught to interface the STA680 with the external an external flash typically used to store the application code. SPI3 - The third SPI allow the HD Radio decoder to control an external SD/MMC card.

For master mode the SPI clock frequency is a divide down by n of the internal peripheral clock frequency, where n is an integer number comprised between 2 and 65536. The maximum SPI clock frequency in master mode is 25 MHz. For slave mode the maximum input frequency value accepted for the SPI clock from an external device is a function of the internal peripheral clock. F perif In particular the maximum frequency is F SPI = -------------- . 8 Figure 11 shows timing diagrams and waveform for the three SPI.
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STA680
Digital I/O and memory interfaces Figure 11. Three SPI timing diagrams and waveform
Tss
SPIx_SS_N
1/Fsck SPIx_SCK cpol =0 Ts SPIx_MOSI/MISO Z D7 D6 D5 D4 D3 D2 D1 Th D0 Z
1/Fsck SPIx_SCK cpol =1 Ts SPIx_MOSI/MISO Z D7 D6 D5 D4 D3 Th D2 D1 D0 Z
AC00718
In Table 10 are reported the timing values for the SPI interface. Table 10.
Symbol Tss Fsck Fsck Th Ts
SPI interface timing values
Working rate Parameter Chip select Serial bit clock, slave mode Serial bit clock, master mode Data hold time Data setup time Condition Min. 8/Fsck 1.076 1.076 7 15 8000 25000 Max. kHz kHz kHz ns ns Unit
5.4.1
Host micro serial peripheral interface (SPI1)
The Host Micro SPI is used as a host processor interface. The usage of this interface is optional because the STA680 is able to communicate with an external microcontroller also via I2C protocol (see Chapter 5.4.5, Host micro I2C interface). The Host Micro SPI is a slave only interface. For pin description see Table 11. Table 11. Host Micro SPI pin list
Designation Host Micro SPI data master in/slave out Host Micro SPI data master out/slave in Host Micro SPI clock Host Micro SPI active-low slave select 1 Type O I O O Drive 4mA 4mA 4mA
Pin name SPI1_MISO (1) SPI1_MOSI
(1)
SPI1_SCK SPI1_SS_N
1. Slave only interface.
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5.4.2
Flash serial peripheral interface (SPI2)
The Flash SPI is useful for storing boot code and other configuration parameters. The minimum required capacity for this purpose is 1 Mbit. The STA680 is SPI master only on the FLASH bus. No glue logic is necessary to connect an external Flash to the HD Radio Decoder. In the BGA package up to 4 chips selects are available. For pin description see Table 12. Table 12. Flash SPI pin list
Designation Flash SPI data master in/slave out Flash SPI data master out/slave in Flash SPI clock Flash SPI active-low slave select 1 Flash SPI active-low slave select 2 (2)) Flash SPI active-low slave select 3 Flash SPI active-low slave select 4
(2) (2)
Pin name SPI2_MISO(1) SPI2_MOSI(1) SPI2_SCK SPI2_SS_N SPI2_SS1_N SPI2_SS2_N SPI2_SS3_N
Type I O O O O O O
Drive 4mA 4mA 4mA 4mA 4mA 4mA
1. Slave only interface. 2. Only available in BGA package.
5.4.3
SD/MMC serial peripheral interface (SPI3)
The SPI SD/MMC SPI allows to connect the STA680 to a Secure Digital Card or a Multimedia Card for data storage purposes. This interface can be configured to be master or slave and is available only in the BGA Package. For pin description see Table 13. Table 13. SD/MMC SPI pin list
Designation(1) SD/MMC SPI data master in/slave out SD/MMC SPI data master out/slave in SD/MMC SPI clock SD/MMC SPI active-low slave select 1 Type I/O I/O O O Drive 4mA 4mA 4mA 4mA
Pin name SPI3_MISO SPI3_MOSI SPI3_SCK SPI3_SS_N
1. Only available in BGA package
5.4.4
I2C interfaces
The STA680 provides two I2C interfaces that can be used to communicate with the Host Microcontroller. The first one may be used by the Host Micro in replacement of the SPI1 to control the main function of the HD Radio Decoder. The second one is an auxiliary interface and is available only in the LFBGA package option. For pin description see Table 14.
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STA680 Table 14. Host and auxiliary I2C interface pin list
Designation Host Micro I2C interface serial clock line Host Micro I C interface serial data line
2 2
Digital I/O and memory interfaces
Pin name IIC1_SCL IIC1_SDA IIC1_DA IIC2_SCL IIC2_SDA IIC2_DA
Type I/O I/O I/O I/O I/O I/O
Drive 4mA 4mA 4mA 4mA 4mA 4mA
Host Micro I C interface data acknowledged Auxiliary I2C interface serial clock line Auxiliary I C interface serial data line Auxiliary I C interface data acknowledged
2 2
The data pins of the two I2C interfaces are open drain drivers and must have resistive pullup conforming to Philip's IIC specification. Figure 12 shows timing diagrams and waveform for the two I2C interfaces. Figure 12. Timing diagrams and waveform for the two I2C interfaces
Th,sta Th,sto
Bit 1 Bit 2 Bit n
IICx_SDA
Ts,dat
IICx_SCL
Thigh Th,dat
Start 1/Fscl Tlow
Stop
AC00719
In Table 15 are reported the timing values for the I2C interface. Table 15.
Symbol Fscl Tlow Thigh Th,dat Ts,dat Th,sta Ts,sto
I2C interface timing values
Standard-mode Parameter Scl clock frequency Low period of scl clock High period of scl clock Data hold time Data setup time Hold time for start condition Setup time for stop condition 4.7 4 5 250 4 4 100 0.6 0.6 Condition Min. Max. 100 1.3 0.6 Min. Max. 400 kHz s s s s s s Fast-mode Unit
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5.4.5
Host micro I2C interface (I2C1)
The Host Micro I2C Interface enables the host processor to pass commands, diagnostic information, and data between the host processor and HD Radio Decoder. The I2C1 interface is a standard I2C interface where the STA680 acts as a slave to the Host Micro and only responds to requests for information. It is also configurable by the Host Micro to work as a master to better support bi-directional flow of data and audio. The I2C1 interface supports 7-bit addressing and 8-bit data. It can run in both standard mode (serial clock frequency up to 100 kHz) and fast mode (up to 400 kHz). The I2C device addresses are reported in Table 16. Although not part of the IIC standard, an additional control line called IIC1_DA is provided. This line is useful for indicating when data is available and can be polled by either master or slave. Table 16. I2C1 interface device address
I2C1 Read Address Write Address Primary address 0101111b 0101110b Secondary address 0101101b 0101100b
5.4.6
Auxiliary I2C interface (I2C2)
The Auxiliary I2C interface can be programmed to be a master or slave. The usage of this interface by the host processor is optional and by default it is disabled after reset. The I2C2 interface supports 7-bit addressing and 8-bit data. It can run in both standard mode (serial clock frequency up to 100 kHz) and fast mode (up to 400 kHz). The I2C device addresses are reported in Table 17. Although not part of the IIC standard, an additional control line called IIC1_DA is provided. This line is useful for indicating when data is available and can be polled by either master or slave. Table 17. I2C2 interface device address
I2C2 Read Address Write Address Primary Address 0101011b 0101010b Secondary Address 0101001b 0101000b
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STA680
Digital I/O and memory interfaces
5.5
SDRAM interface
The SDRAM interface supports up to 32M x 16 SDRAM and supports both standard and mobile protocols. For pin description see Table 18 Table 18. SDRAM Interface pin description
Designation SDRAM interface data bus SDRAM interface address bus Bank address Active-low column address strobe Active-low row address strobe Active-low write enable Active-low chip select low-byte data input/output mask high-byte data input/output mask Clock enable Clock to SDRAM for 3.3 V interface Feedback clock from SDRAM Type I/O O O O O O O O O O O I Drive 4 mA 4 mA 4 mA 8 mA 8 mA 8 mA 8 mA 4 mA 4 mA 4 mA 8 mA 8 mA
Pin Name SDR_D[0:15] SDR_A[0:12] SDR_BA[0:1] SDR_CAS_N SDR_RAS_N SDR_WE_N SDR_CS_N SDR_DQM0 SDR_DQM1 SDR_CKE SDR_CLK_RAM3V3 SDR_FEED_CLK
The minimum required SDRAM size for single channel application is 64 Mbit while for a dual channel application at least 128 Mbit are needed. Figure 13 shows timing diagrams and waveform for the SDRAM interface. Figure 13. Timing diagrams and waveform for the SDRAM interface
Tck Tch
SDR_CLK_RAM
Tcl
SDR_CLK_CS SDR_RAS
SDR_CAS
SDR_WE_N SDR_BA SDR_A SDR_D
CAS latency = 3
BANK
BANK
BANK
BANK
ROW Tds
COL Tdh Din
ROW
COL
Tac
Toh
Dout
write
read
AC00720
In Table 19 are reported the timing values for the SDRAM interface.
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Digital I/O and memory interfaces Table 19.
Symbol Tck Tch Tcl Tdh Tds Tac Toh Tt
STA680
SDRAM interface timing values
Parameter SCL clock period CLK high level width CLK low level width Data hold time Data setup time Access time from clock (posedge) Data out hold time Transition time Condition Min. 6.06 2.5 2.5 2 2 1.8 Max. 5.4 1.2 Unit ns ns ns ns ns ns ns ns
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STA680
Electrical specifications
6
6.1
Electrical specifications
Absolute maximum ratings
Table 20. Absolute maximum ratings
Parameter Core supply voltage Generic IO supply voltage Flash IO supply voltage SDRAM IO supply voltage Osc 1V8 supply voltage Pll analog supply voltage Pll digital supply voltage Saf core supply voltage Voltage on input pin Voltage on output pin Operative storage temperature Operative junction temperature Operative ambient temperature Value 1.3 3.6 3.6 3.6 1.95 2.75 1.3 1.3 -0.5 to (VDDIO* + 0.5) -0.5 to (VDDIO* + 0.5) -40 to +150 -40 to +125 -40 to +85 Unit V V V V V V V V V V C C C Symbol VDD VDD_GEN_IO VDD_FSH_IO VDD_RAM_IO VDD_OSC VDD_PLL_ANA VDD_PLL_DIG VDD_SAF Vi Vo Tstg Tj Tamb
6.2
Thermal data
Table 21.
Symbol Rth j-amb
Thermal data
Parameter Thermal resistance junction to ambient(1) LQFP 30 LFBGA 35 Unit C/W
1. According to JEDEC specification on a 4 layers board.
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Electrical specifications
STA680
6.3
Table 22.
Symbol VDD
Operating conditions
DC electrical characteristics
Parameter Core supply voltage Generic IO supply voltage Flash IO supply voltage SDRAM IO supply voltage Oscillator analog supply voltage Test condition Min. 1.1 3.0 3.0 3.0 1.7 1.7 1.1 1.1 Typ. 1.2 3.3 3.3 3.3 1.8 1.8 1.2 1.2 Max. 1.3 3.6 3.6 3.6 1.95 2.75 1.3 1.3 Unit V V V V V V V V mA mA mW Vi = 0V Vi = VDD_GEN_IO(2) Vi = VDD_GEN_IO(2) Vi = 0V Vi = 0V Vi = VDD_GEN_IO Vi = 0V Vi = VDD_GEN_IO(2) 3.3 supply mode 3.3 supply mode 3.3 supply mode Ioh =XmA(7) Iol =XmA(7)
(2)
VDD_GEN_IO VDD_FSH_IO VDD_RAM_IO VDD_OSC
VDD_PLL_ANA PLL analog supply voltage VDD_PLL_DIG PLL digital supply voltage VDD_SAF IDD_1V2 IDD_IO Pd Iil Iih Ilpu Ilpd Ipu Ipd Rpu Rpd Vil Vih Vhyst Voh Vol SAF supply voltage Core supply current at 1.2V IO supply current Power dissipation Low level input leakage current(1) High level input leakage current(1) High level input leakage current on pull up(3) Low level input leakage current on pull-down(4) Pull-up current Pull-down current Equivalent pull-up resistance(5) Equivalent pull-down resistance(6) Low level input voltage High level input voltage Input hysteresis voltage Output high voltage Output low voltage
1.9 1.9 2.9 10 72 72 50 50 -0.3 2.0 50 VDD_R AM_IO - 0.2V 0.2 0.8 VDD_G EN_IO +0.3
A A A A A A K K V V mV V V
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STA680 Table 22.
Symbol
Electrical specifications DC electrical characteristics (continued)
Parameter Test condition Human Body Model Min. Typ. Max. 2000 200 500 100 3.0 Vi = 0V Vi = VDD_RAM_IO Vi = VDD_RAM_IO Vi = 0V Vi = 0V Vi = VDD_RAM_IO Vi = 0V Vi = VDD_RAM_IO 44 29 29 29 0.8 2 300 Ioh = -XmA(7) Iol =XmA(7) VDD_R AM_IO 0.3 0.3 800 122 122 67 103 3.3 3.6 Unit V V V mA V A A A A A A K K V V mV V V
Vesd
Electrostatic discharge voltage Machine Model Charge device Model
Ilatchup VDD_RAM_IO Iil_ram Iih_ram Ilpu_ram Ilpd_ram Ipu_ram Ipd_ram Rpu_ram Rpd_ram Vil_ram Vih_ram Vhyst_ram Voh_ram Vol_ram
Injection current SDRAM IO supply voltage Low level input leakage current(1) High level input leakage current(1) High level input leakage current on pull up(3) Low level input leakage current on pull-down(4) Pull-up current Pull-down current Equivalent pull-up resistance(5) Equivalent pull-down resistance(6) Low level input voltage High level input voltage Schmitt trigger hysteresis High level output voltage Low level output voltage
Maximum operating junction temperature 125 C
1. Performed on all the input pins excluded the pull-down and pull-up ones. 2. VDD_GEN_IO may be VDD_FHS_IO or VDD_GEN_IO depending on interface considered. 3. Performed only on the Input pins with pull up. 4. Performed only on the Input pins with pull down. 5. Guaranteed by Ipu measurements. 6. Guaranteed by Ipd measurements. 7. XmA = 4mA for a BD4, 8mA for BD8 pad type.
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Package information
STA680
7
Package information
In order to meet environmental requirements, ST (also) offers these devices in ECOPACK(R) packages. ECOPACK(R) packages are lead-free. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 14. LQFP144 (20x20mm) mechanical data and package dimensions
mm DIM. MIN. A A1 A2 b c D D1 D3 E E1 E3 e L L1 k ccc 0.450 0.050 1.350 0.170 0.090 1.400 0.220 TYP. MAX. 1.600 0.150 0.0020 MIN. TYP. MAX. 0.0630 0.0059 inch
OUTLINE AND MECHANICAL DATA
1.450 0.0531 0.0551 0.0571 0.270 0.0067 0.0087 0.0106 0.200 0.0035 0.0079
21.800 22.000 22.200 0.8583 0.8661 0.8740 19.800 20.000 20.200 0.7795 0.7874 0.7953 17.500 0.6890
21.800 22.000 22.200 0.8583 0.8661 0.8740 19.800 20.000 20.200 0.7795 0.7874 0.7953 17.500 0.500 0.600 1.000 0.6890 0.0197 0.750 0.0177 0.0236 0.0295 0.0394
0(min.), 3.5(typ.), 7(max.) 0.080 0.0031
LQFP144 (20x20x1.40mm) Low profile plastic Quad Flat Package
Note 1: Exact shape of each corner is optional.
0099183 C
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STA680
Package information Figure 15. LFBGA 168 balls (12x12x1.4 mm) mechanical data and package dimensions
mm DIM. MIN. A A1 A2 A4 b D D1 E E1 e Z ddd eee fff 0.350 0.400 0.210 0.200 0.800 TYP. MAX. 1.400 0.0083 0.0078 0.0315 MIN. TYP. MAX. 0.0551 inch
OUTLINE AND MECHANICAL DATA
0.450 0.0138 0.0157 0.0177
11.850 12.000 12.150 0.4665 0.4724 0.4783 10.400 0.4094
11.850 12.000 12.150 0.4665 0.4724 0.4783 10.400 0.800 0.800 0.100 0.150 0.080 0.4094 0.0315 0.0315 0.0039 0.0059 0.0031
Body: 12 x 12 x 1.4mm
LFBGA 168 balls Low profile Fine Pitch Ball Grid Array
8123111 B
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Revision history
STA680
8
Revision history
Table 23.
Date 25-Jul-2008
Document revision history
Revision 1 Initial release. Changes
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STA680
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